The invention broadly relates to programmable logic devices (PLD). More particularly, the invention relates to a high speed, zero DC power PLD architecture.
Programmable logic devices (PLD) are well known in the art and are widely used to perform complex digital logic functions in the form of a sum of products, or a product of sums. Fundamentally, each PLD includes a memory array or matrix functioning as an programmable AND gates, a sensing circuitry, an array of fixed OR gates, and output logic circuits. The array of fixed OR gates can be also be a programmable OR array. When the row and column decoders select a specific cell from which to read or write data, a sense amplifier in the sensing circuitry reads the information from the selected cell and the fixed OR array and the output logic circuits to perform the logic function. When this happens, the bitlines of the programmable array connected to the selected cell is pulled low, or has high impedance. The sense amplifiers read out the information contained in that cell and pass it to the array of OR gates and then to the output logic circuits as outputs of the PLD.
With reference to FIG. 1A, a typical prior art programmable logic device (PLD) 100A comprises a programmable array 110 arranged in rows 102 and columns 104. The intersection of each row and column is a cell 106 and is programmed by either one-time fuselink method or by a floating-gate CMOS. The floating-gate CMOS cells can be UV or electrical erasable. The programmable array 110 is coupled to an array of sense amplifiers 120. The sense amplifiers 120 read the content of each of the selected cells and pass the information to an array of fixed OR gates 130. The array of fixed OR gates 130 is coupled to the output logic circuits 140. The output logic circuits 140 are usually clocked sequential circuits to latch out the outputs. This type of PLD is well-known in the art and is called a programmable array logic (PAL).
The sense amplifiers 120 of the PAL 100A consume a significant amount of power. When the PLD 100A is in the standby mode, the sense amplifiers 120 have to be ON so that they can read the contents of the selected cells when the PLD 100A is powered up. In this standby mode, sense amplifiers draw hundreds of milliamperes. Furthermore, the prior art PLD 100A has to go through several different stages such as the programmable array 110, the sense amplifier array 120, the array of fixed OR gates 130, and the logic output circuits 130 to complete the operation. This type of architecture is rather slow.
Another type of PLD is a programmable logic array (PLA) shown in FIG. 1B. The PLA 100B has a programmable array 110B, a first array of sense amplifiers 120B, a programmable OR array 130B, a second array of sense amplifiers represented by 140B) to read information from the programmable OR array 130B, and output logic circuits 150B. The PLA 100B is more flexible but slower in speed and consumes more power than the PAL 100A.
The number of conducting cells in the programmable array determines the speed and the power consumption of each PLD. The speed of each PLD depends on the number of cells that the sense amplifiers read. The speed also depends on the architecture of the PLD: the larger the programmable array, the slower the speed.
Ordinarily, in the standby mode, a PLD consumes about 100 mA of current to set the PLD chip ready for the next action. There is a need to reduce this power consumption because it shortens the life of a battery in products in which the PLD is used. Moreover, sense amplifiers consume a substantial amount of power during normal operation. Additionally, noise spikes often cause the PLD to read incorrect values to its output logic circuits. Therefore, there is a need to improve power consumption, speed, and noise immunity in PLD architecture.
There have been numerous attempts in the prior art to improve these performance factors in PLDs. U.S. Pat. No. 5,568,066 discloses a high density programmable logic device (PLD) including sense amplifiers and OR gates configured to increase speed, reduce number of transistors, and provide a selectable power-down mode. To achieve these features, the ""066 patent uses sense amplifiers including a single cascode amplifier in the data path to connect a product term to the OR gates. The OR gates utilize a plurality of source-follower transistors followed by pass gates to provide logic allocation enabling the sense amplifier output to reduce from the 0 to 5 volts CMOS rails to increase switching speed while reducing transistor count. Amplifying inverters, normally provided in the sense amplifiers to provide the CMOS rail-to-rail switching and which would require complex feedback for providing power down on a macrocell-by-macrocell basis, are moved forward into OR output circuits. Power-down on a macrocell-by-macrocell basis is provided by selectively sizing the amplifying inverters in the output circuits. The ""066 patent teaches a reduction of the number of transistors and a rail-to-rail voltage swing without a feedback mechanism.
U.S. Pat. No. 5,734,275 discloses a programmable logic device (PLD) having an improved sense amplifier. The sense amplifier comprises a cascode pair of transistors coupled between a sense amplifier output and a virtual ground. A clipping and current channeling transistor can also be provided with the sense amplifier to improve its noise performance. The clipping transistor helps ensure the any positive-going noise spikes do not deleteriously affect the accurate threshold triggering value of the input line. The current channeling transistor helps prevent collapse of a bit caused by significant conductivity of cells connected to the bitline. The combination of clipping and current channeling provides a relatively narrow voltage range of the bitline voltage, resulting in fast recovery and high speed sensing. The additional current source is used to impute additional current through the amplifying transistor of the cascode-coupled pair of transistors. The additional current sink transistor helps draw the current from the amplifying transistor to a ground supply. Only when a bitline is high will the additional current source and current sink be used. However, the ""275 patent teaches improved sensing speed of the sense amplifier by providing a narrow voltage range of the bitline voltage. The noise performance of the circuit described in the ""275 patent improves by clipping the positive going noise to avoid falsely triggering the sense amplifier.
Another attempt to solve the power consumption and speed in a PLD is disclosed in U.S. Pat. No. 5,532,623. In this patent, a sense amplifier includes a pull-down device which contains a reference cell which is structurally identical to the PLD cells being sensed and a pull-up device connected to form a current mirror which causes a saturation current of the pull-up device to be zero or greater than the current through the sensed-cell. The pull-down device has a saturation current which tracks the current through the sensed cell, saturation current through the pull-up device exceeds that of the pull-down device, and an output node is pulled up. When no current flows through the sensed cell, no current flows through the pull-up device, and the pull-down device pulls the output node down. As a result, the sense amplifier exhibits a variable trip point which tracks variations caused by changes in the device fabrication process, temperature, and power supply voltage. The reference cell in the sense amplifier conducts a current only during sensing, and therefore consumes no standby power. The ""630 patent uses the reference cell and pull-up, pull-down devices to limit the flow of current into the sense amplifier to reduce the standby power consumption to zero.
It is the object of the present invention to provide an improved PLD architecture that has low overall power consumption, high speed, and good noise immunity.
The above objects have been achieved in a high speed programmable logic device (PLD) architecture that is implemented entirely in CMOS components arranged so that the device does not use power in a standby mode. According to one embodiment of the invention, the PLD comprises a plurality of programmable logic device (PLD) single-bit cells forming a programmable array. Each PLD single-bit cell is the basic building block of the programmable array. From a PLD single-bit cell, any Mxc3x97N programmable OR or AND array can be implemented. Each PLD single-bit cell combines a single-bit memory cell and a sense amplifier together so that the PLD does not have to traverse through the selected cells and read them into the sensing circuitry as prior art PLDs.
Each PLD single-bit cell of the present invention includes a settable latch, a programmable cell unit, an output logic gate, and a signal-path means coupled between the programmable cell unit and the output logic gate for providing a positive feedback thereto. The device further comprises an array of OR gates and an output sequential circuits. Preferably, each column of the programmable AND array is a bit-by-44 cell whose output is coupled to the array of OR gates. The array of OR gates is coupled to the output logic circuit for outputs of the PLD. Each bit-by-44 cell gate further comprises of two bit-by-16 cells and one bit-by-12 cell. Each bit-by-16 cell further comprises four bit-by-4 cells, and each bit-by-12 cell comprises three bit-by-4 cells. A bit-by-4 cell comprises a four PLD single bit cells. The array of OR gates can be either fixed or programmable.